5 V expansion-board supply
To supply an expansion-board module at 5 V, execute this setting at the very start of the program. After configuration, only P8/P9 can output 5 V; other I/O outputs are limited to 3.3 V.
*(volatile int*)0x40080124 = 0x1d;
CP8101 SoC (datasheet)
Source: CP8101 Datasheet v1.0.4, pages 2–3, 7 and 11–12. These are chip data, not CP81-MINI board measurements.
Processor32-bit RISC-V, up to 48 MHz
Wireless capabilityChip supports Bluetooth LE 5.3 and a proprietary 2.4 GHz protocol; board RF implementation remains unverified
RF band2,400–2,483.5 MHz (datasheet table 3-5)
BLE radio data ratesDatasheet lists 1 and 2 Mbps plus 500 and 125 kbps; firmware modes and actual throughput remain unverified
Chip low-power referencesDatasheet lists 1 μA sleep and 10 μA BLE connection maintenance at a 1 s interval; neither is whole-board current
RF figures-25 to +12 dBm TX power; typical -98.2 dBm RX sensitivity at 1 Mbps (0.1% BER, conducted test)
Memory16 KB SRAM, 64 KB ROM, 16 KB OTP, 4 KB instruction cache; populated board Flash remains unconfirmed
PeripheralsUp to 15 GPIO; 2 UART, 2 SPI, 1 I²C, QSPI; 10-bit ADC and hardware AES-128
Chip voltage and temperatureRecommended VDD 1.8–5.5 V; use at 5.5 V requires software configuration. Operating temperature -40 to +105 °C. Not a board power rating
Package / modelQFN20; datasheet lists CP8101-QA23, while the populated board part number remains unconfirmed
CP81-MINI board pinout
Pin names and physical order follow the supplied board photos. UART, PWM, I²C, ADC, SPI and voltage notes follow the RD pin-definition diagram supplied on 2026-09-21. The outlined front and back illustrations derive from STEP V1.0.3 geometry.
Both views place USB-C at the top. The front is the component side; the left and right rows swap when the board is viewed from underneath. Table positions 1–9 count down from the USB end and are geometric positions, not JP1/JP2 schematic pin numbers.
On phones, swipe sideways to see every pin; tap an image to open it full size.
The diagram and table list every UART, PWM, I²C, ADC and SPI alternate function shown in the RD pin-definition diagram. I²C indicates an available multiplexed function and does not assign SDA or SCL; firmware selects the role and initialization. P8/P9 marked 5V I/O* must follow the setup and voltage restrictions below.
RD wiring and voltage notes
The following is transcribed from the RD screenshot supplied on 2026-09-21. Register writes and 5 V operation must be limited to the corresponding hardware and SDK revision; verify the peripheral and supply before wiring.
5 V I²C
When I²C communication requires 5 V signaling, use only P8/P9. The RD note identifies P8/P9 as the only 5 V I/O.
P0/P23 power-up notes
P0 has one transition at power-up. For P23, RD instructs clearing bit[12] of 0x4008000C.
*(volatile int *)(0x4008000C) &= ~(1<<12);The 18 holes and outline come from STEP. Metallic contact color and the front-chip logo/CP8101 marking are visual treatments; STEP does not include actual underside traces or silkscreen. Alternate functions and voltage notes come from the RD pin-definition diagram; the website team has not yet completed per-pin electrical and firmware validation.
| Position from USB | Front leftRD alternate functions | Front rightRD alternate functions |
|---|---|---|
| 1 | P7UART1 · PWM7 · I²C · ADC2 | 5V |
| 2 | P8UART0 RX · PWM0 · I²C · 5V I/O* | GND |
| 3 | P9UART0 TX · PWM1 · I²C · 5V I/O* | 3V3 |
| 4 | P15UART1 · I²C · ADC4 | P6ADC1 · I²C · PWM6 · UART1 |
| 5 | P18UART1 · PWM2 · I²C · SPI | P5I²C · PWM5 · UART1 |
| 6 | P19UART1 · PWM3 · I²C · ADC6 · SPI | P4I²C · PWM4 · UART1 |
| 7 | P20UART1 · PWM4 · I²C · SPI | P2I²C · PWM2 · UART1 |
| 8 | P21UART1 · PWM5 · I²C · SPI | P1I²C · PWM1 · UART1 |
| 9 | P23UART1 · PWM7 · I²C | P0I²C · PWM0 · UART1 |
5V, 3V3 and GND are the 5 V supply contact, 3.3 V supply contact and ground reference. RD further states that P8/P9 can operate as 5 V I/O after the specified register setup; other GPIO outputs are limited to 3.3 V. This does not make every GPIO 5 V tolerant. Available current, protection and power direction still require a board specification.
External contacts18 total, nine per side; GPIO alternate functions follow the newly supplied RD pin-definition diagram
Model outlineBoard geometry in STEP V1.0.3 spans about 18 × 23.5 mm; physical dimensions await verification
Populated Flash, available supply current, protection, USB and wireless implementationPending updated board specifications and physical validation